1. Field of the Invention
This invention relates to magnetic memory arrays and, more particularly, to data line configurations within magnetic memory cells.
2. Description of the Related Art
The following descriptions and examples are given as background information only.
Recently, advancements in the use of magnetoresistive materials have progressed the development of magnetic random access memory (MRAM) devices to function as viable non-volatile memory circuits. In general, MRAM circuits exploit the electromagnetic properties of magnetoresistive materials to set and maintain information stored within individual magnetic memory cell junctions of the circuit. In particular, MRAM circuits utilize magnetization direction to store information within a magnetic junction, and differential resistance measurements to read information from the magnetic junction. Typically, an MRAM circuit includes a plurality of conductive lines with which to generate magnetic fields such that the magnetic directions of one or more magnetic junctions of the MRAM circuit may be set. Consequently, the conductive lines may be referred to as “field-inducing lines,” in some embodiments.
Typically, the conductive lines are formed as substantially straight and uniform structures of metal spaced perpendicular to each other within a plane comprising the magnetic cell junction. In other words, the conductive lines may be arranged in series of columns and rows having magnetic junctions interposed at the overlap points of the conductive lines. In this manner, the device may include a plurality of memory cells aligned within an array. In some cases, the conductive lines may be referred to as “bit” and “digit” lines. In such an embodiment, “bit” lines may refer to the conductive lines that are arranged in contact with magnetic junctions and which are used for both write and read operations of the cell. “Digit” lines, on the other hand, may refer to the conductive lines spaced adjacent to the magnetic junctions and used primarily during write operations of the cell.
In general, an individual magnetic junction can be written to by applying current simultaneously along a bit line and a digit line corresponding to the particular magnetic junction. Such an individual magnetic junction may herein be referred to as a selected magnetic junction, or the magnetic junction intentionally targeted for a writing procedure. During the writing procedure, however, the multitude of magnetic junctions arranged along the bit line and the digit line corresponding to the selected junction will also sense current. Such magnetic junctions are herein referred to as half-selected junctions, or disturbed junctions since the magnetic field induced about them is generated from either a bit line or a digit line rather than from both a bit line and a digit line. Even though less current is applied to these disturbed cells, variations within the magnetic junctions may allow the magnetic field induced by the low current to switch the magnetic directions of one or more of the disturbed cells. In this manner, the write selectivity of the array may be reduced. Write selectivity, as used herein, may refer to the relative difference (i.e., current margin) between the amount of current responsible for switching the magnetization of a disturbed cell and the amount of current needed to switch the magnetization of a selected cell. Consequently, a reduction in write selectivity reduces the tolerance of the current used to reliably switch selected cells without switching disturbed cells within an array. In some cases, the tolerance may too small, allowing a false bit to be unintentionally written to one or more of the disturbed cells and in turn, decreasing the reliability of the array.
In addition, the number of memory cells arranged within an array may be limited by the arrangement of the conductive lines spanning across the columns and rows of the array. In general, the voltage required to generate a desired amount of current along a conductive line increases as the length of a conductive line increases, due to the current-resistance (IR) drop along the line. Since it is desirable to limit the overall power requirements of an array and, therefore, the amount of voltage used to operate the array, the conductive lines are generally restricted in length. Consequently, the number of magnetic junctions within an array is limited. Such a restriction limits the number of devices on a chip, thereby limiting the memory capacity of the integrated circuit.
Therefore, it would be advantageous to develop a magnetic memory array with a configuration that reduces the effect of IR drop on the size of a memory array. In particular, it may be advantageous to fabricate a magnetic memory array with a configuration that eliminates IR drop as a limiting factor for the number of memory cells arranged along at least one dimension of an array. Such an array may advantageously increase the density of memory cells, thereby increasing the number of devices on a chip. In addition, it would be advantageous to develop a magnetic memory array with a configuration that increases the write selectivity of a magnetic memory array. More specifically, it would be advantageous to develop a magnetic memory array with a configuration that eliminates the issue of write selectivity.